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CS5460 Datasheet(PDF) 17 Page - Cirrus Logic |
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CS5460 Datasheet(HTML) 17 Page - Cirrus Logic |
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17 / 34 page ![]() CS5460 DS279PP5 17 3.1.7 Register Read/Write Command This command informs the state machine that a register access is required. On reads the addressed register is loaded into the output buffer and clocked out by SCLK. On writes the data is clocked into the input buffer and transferred to the addressed register on the 24th SCLK. W/R Write/Read control 0 = Read register 1 = Write register RA[4:0] Register address bits. Binary encoded 0 to 31. All registers are 24 bits in length. Address Name Description 00000 Config Configuration Register 00001 Ioff Current offset calibration 00010 Ign Current gain calibration 00011 Voff Voltage offset calibration 00100 Vgn Voltage gain calibration 00101 Cycle Count Number of conversions to integrate over (N) 00110 Pulse-Rate Used to calibrate/scale the energy to frequency output 00111 I Last current value 01000 V Last voltage value 01001 P Last Power value 01010 E Total energy value of last cycle 01011 IRMS RMS current value of last cycle 01100 VRMS RMS voltage value of last cycle 01101 TBC Timebase Calibration 01110 Test Internal Use only † 01111 Status Status register 10000 Res Reserved . . 10111 Res Reserved 11000 Test Internal Use only † 11001 Test Internal Use Only † 11010 Mask Interrupt mask register 11011 Test Internal Use Only † 11100 Res Reserved . . 11111 Res Reserved † These Registers are for Internal Use only and should not be written to. Accessing these registers will NOT generate an “Invalid Command” (IC) bit in the Status Register. B7 B6 B5 B4 B3 B2 B1 B0 0W/R RA4 RA3 RA2 RA1 RA0 0 |
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