CS5460

24

DS279PP5

4.8 Timebase Calibration

Address: RA[4:0]* = 0x0D

Default** = 1.000

The Timebase Register is initialized to 1.0 on reset, allowing the device to function and perform computations.

The register is user loaded with the clock frequency error to compensate for a gain error caused by the crys-

tal/oscillator tolerance. The value is in the range 0.0

≤ TBC < 2.0.

4.9 Status Register and Mask Register

Address:

RA[4:0]* = 0x0F (Status Register)

RA[4:0]* = 0x1A (Mask Register)

Default** = 0x000001 (Status Register)

0x000000 (Mask Register)

The Status Register indicates the condition of the chip. In normal operation writing a ’1’ to a bit will cause the bit

to go to the ’0’ state. Writing a ’0’ to a bit will maintain the status bit in its current state. With this feature the user

can simply write back the status register to clear the bits that have been seen, without concern of clearing any

newly set bits. Even if a status bit is masked to prevent the interrupt, the status bit will still be set in the status

register so the user can poll the status.

The Mask Register is used to control the activation of the INT pin. Placing a logic ’1’ in the mask register will

allow the corresponding bit in the status register to activate the INT pin when the status bit becomes active.

IC

Invalid Command. Normally logic 1. Set to logic 0 when the part is given an invalid command.

Can be deactivated only by sending a port initialization sequence to the serial port. When writing

to status register this bit is ignored.

LSD

Low Supply detect. Set when the PFMON pin falls below 2.5 volts with respect to the VA- pin.

IOD

Modulator oscillation detect on the current channel. Set when the modulator oscillates due to

an input above Full Scale.

VOD

Modulator oscillation detect on the voltage channel. Set when the modulator oscillates due to

an input above Full Scale.

WDT

Watch-Dog Timer. Set when there has been no reading of the Energy register for more than 5

seconds. (MCLK = 4.096 MHz, K = 1) To clear this bit, first read the Energy register, then write

to the status register with this bit set to logic ’1’.

EOOR

EOUT energy/current summing register went out of range. This can be caused by having an

output rate that is too small for the power being measured. The problem can be corrected by

specifying a higher frequency in the pulse-rate register.

MSB

LSB

.....

23

22

21

20

19

18

17

16

DRDY

EOUT

EDIR

Res

MATH

Res

IOR

VOR

15

14

13

12

11

10

9

8

PWOR

IROR

VROR

EOR

EOOR

Res

Res

Res

765

4321

0

Res

Res

WDT

VOD

IOD

LSD

0

IC