DA7218 datasheet(61/154 Pages) RENESAS

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Ultra-Low Power Stereo Codec

R32DS0004EE0370 Revision 3.7

Aug 9, 2024

CFR0011-120-00

Page 61

maximum), and SYS_CLK/16, /32, /64 and /128. Where SYS_CLK is 12.288 MHz or 11.2896 MHz depending on

sample rate.

If cp_mchange does not = 00, the charge pump load is monitored and the clock frequency adjusted accordingly

to allow the charge pump to supply the required current. Clock frequency varies depending on the charge pump

requirements, and the cp_fcontrol settings specify the minimum frequency at which the clock will run. The

maximum frequency is always SYS_CLK/8.

In addition to the cp_fcontrol settings outlined above, and which specify the minimum clock frequency, there is

an extra setting of cp_fcontrol = 101 which has no minimum frequency. At this setting, the clock frequency is

under the complete control of the tracking and feedback mechanism. The frequency can vary from 0 Hz when

there is no load on the charge pump and no component leakage, up to the maximum of SYS_CLK/8.

In general this setting can be left at its default value of 001.

9.4.9

Other Charge Pump Controls

When a higher charge pump output voltage is needed, the charge pump increases its output at the fastest rate

possible given the controls and settings in that currently in place. Once the higher output voltage is no longer

needed, the charge pump controller waits for a period determined by the cp_tau_delay setting before reducing

the output voltage.

For best performance, Renesas recommend setting cp_tau_delay to 16 ms or greater.

cp_small_switch_freq_en enables a low-load, low-power switching mode. If cp_small_switch_freq_en is enabled

and cp_fcontrol is set to a value between 000 and 100, any feedback from the analog level detector results in a

switch from low-power to full-power. Full-power is maintained for one cp_tau_delay period after the pulse, any

subsequent pulses restart the cp_tau_delay period.

If cp_fcontrol = 101, the first feedback from the analog level detector primes the change to full-power mode. If

another pulse occurs within 32 clock cycles of the first feedback from the analog level detector, full power is

enabled for one cp_tau_delay period.

9.4.10

True-Ground Supply Mode

In true-ground supply mode, the charge pump must be enabled to generate the ground-centered supply rails for

the amplifiers.

9.5

Phase Locked Loop

The DA7218 contains a Phase Locked Loop (PLL) that can be used to generate the required 11.2896 MHz or

12.288 MHz internal system clock when a frequency of between 2 and 54 MHz is applied to MCLK. This allows

sharing of clocks between devices in an application, reducing total system cost. For example, the codec may

operate from common 13 MHz or 19.2 MHz system clock frequency.

9.5.1

PLL Bypass Mode

If an MCLK signal (of [11.2896, 12.288, 22.5792, 24.576, 45.1584, or 49.152] MHz) that is synchronous with

WCLK and BCLK is available, the PLL is not required and should be disabled to save power. PLL bypass mode

is activated by setting pll_mode = 00.

In this mode the PLL is bypassed and an audio frequency clock is applied to the MCLK pin of the codec. The

required clock frequency depends on the sample rate at which the audio DACs and ADCs are operating. These

clock frequencies are summarized in Table 46 for the range of DAC and ADC sample rates that can be

configured using the SR register.

Table 46: Sample rate control register and corresponding system clock frequency

Sample rate, FS (kHz)

SR register

System clock frequency (MHz)

0001

12.288

11.025

0010

11.2896

0011

12.288

0101

12.288

22.05

0110

11.2896

DA7218 Datasheet(PDF) 61 Page - Renesas Technology Corp

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