DA7218 datasheet(97/154 Pages) RENESAS

97 / 154 page

Ultra-Low Power Stereo Codec

R32DS0004EE0370 Revision 3.7

Aug 9, 2024

CFR0011-120-00

Page 97

Bit

Mode

Symbol

Description

Reset

4:3

R/W

hpldet_jack_debounce

HPL jack detection debounce control.

Number of debounce measurements taken before a jack

insertion is confirmed and the host is informed.

Debounce measurements are separated by the time

defined by accdet_jack_rate, so it will take up to

accdet_jack_rate*accdet_jack_deb to successfully

determine a jack insertion. No debouncing is performed

for removal.

00 = no debounce

01 = 2

10 = 3

11 = 4

0x1

2:0

R/W

hpldet_jack_rate

Time between jack detection measurements when there

is no jack or a 3-pole jack is inserted

0 = 5 us

1 = 10 us

2 = 20 us

3 = 40 us

4 = 80 us

5 = 160 us

6 = 320 us

7 = 640 us

0x3

Table 135: HPLDET_CTRL (Page 0: 0x000000D9)

Bit

Mode

Symbol

Description

Reset

R/W

hpldet_discharge_en

Control of automatic discharge of MICBIAS on jack

removal

0 = Disabled

1 = Enabled

0x0

R/W

hpldet_hyst_en

HPL detection hysteresis control

0 = Disabled

1 = Enabled

0x0

R/W

hpldet_comp_inv

HPL detector output inversion control

Setting this register causes the HPL detector comparator

output signal tobe inverted

0 = Not inverted

1 = Inverted

0x0

Table 136: HPLDET_TEST (Page 0: 0x000000DA)

Bit

Mode

Symbol

Description

Reset

hpldet_comp_sts

HPLDET Comparator output

0 = No headphone detected

1 = Headphone detected

0x0

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