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ECP2 Datasheet(PDF) 35 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 35 Page - Lattice Semiconductor |
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35 / 386 page  2-32 Architecture Lattice Semiconductor LatticeECP2/M Family Data Sheet By combining input blocks of the complementary PIOs and sharing some registers from output blocks, a gearbox function can be implemented, which takes a double data rate signal applied to PIOA and converts it as four data streams, IPOS0A, IPOS1A, IPOS0B and IPOS1B. Figure 2-29 shows the diagram using this gearbox function. For more information about this topic, please see information regarding additional documentation at the end of this data sheet. The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade- quate timing when data is transferred from the DQS to the system clock domain. For further information about this topic, see the DDR Memory section of this data sheet. Figure 2-29. Input Register Block for Left, Right and Bottom Edges Clock Transfer Registers Clock Transfer Registers SDR & Sync Registers D1 D2 D0 DDR Registers D Q D-Type D Q D-Type D Q D-Type D Q D-Type /LATCH D Q D-Type 0 1 D Q D Q 0 1 Fixed Delay Dynamic Delay DI (From sysIO Buffer) DI (From sysIO Buffer) INCK** INDD IPOS0A QPOS0A IPOS1A QPOS1A DEL [3:0] CLK0 (of PIO A) Delayed DQS 0 1 CLKA DQ D Q D Q 0 1 0 1 D Q D Q 0 1 D Q D Q 0 1 Fixed Delay Dynamic Delay INCK** INDD IPOS0B QPOS0B IPOS1B QPOS1B DEL [3:0] CLK0 (of PIO B) Delayed DQS CLKB /LATCH True PIO (A) in LVDS I/O Pair Comp PIO (B) in LVDS I/O Pair D-Type* D-Type* D-Type /LATCH D-Type /LATCH D-Type* D-Type* From Routing To Routing D1 D2 D0 DDR Registers SDR & Sync Registers 0 1 DDRSRC Gearbox Configuration Bit DDRCLKPOL DDRCLKPOL *Shared with output register **Selected PIO. Note: Simplified version does not show CE and SET/RESET details From Routing To Routing To DQS Delay Block** To DQS Delay Block** D-Type D-Type D-Type |
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