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ECP2 Datasheet(PDF) 98 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 98 Page - Lattice Semiconductor |
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98 / 386 page ![]() 3-46 DC and Switching Characteristics Lattice Semiconductor LatticeECP2/M Family Data Sheet Figure 3-16. sysCONFIG Slave Serial Port Timing Figure 3-17. Power-On-Reset (POR) Timing Figure 3-18. Configuration from PROGRAMN Timing CCLK (input) DIN DOUT t SUSCDI t HSCDI t CODO t SSCL t SSCH CCLK 2 DONE VCC / VCCAUX / VCCIO81 CFG[2:0] 3 t ICFG Valid INITN t VMC 1. Time taken from VCC, VCCAUX or VCCIO8, whichever is the last to cross the POR trip point. 2. Device is in a Master Mode (SPI, SPIm). 3. The CFG pins are normally static (hard wired). DONE CCLK CFG[2:0] 1 USER I/O INITN PROGRAMN t PRGMRJ t DINIT t DPPINIT t DINITD t IODISS Valid 1. The CFG pins are normally static (hard wired) |
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