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ECP2 Datasheet(PDF) 96 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 96 Page - Lattice Semiconductor |
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96 / 386 page  3-44 DC and Switching Characteristics Lattice Semiconductor LatticeECP2/M Family Data Sheet LatticeECP2/M sysCONFIG Port Timing Specifications Over Recommended Operating Conditions Parameter Description Min. Max. Units sysCONFIG Byte Data Flow tSUCBDI Byte D[0:7] Setup Time to CCLK 7 — ns tHCBDI Byte D[0:7] Hold Time to CCLK 1 — ns tCODO CCLK to DOUT in Flowthrough Mode — 12 ns tSUCS CSN[0:1] Setup Time to CCLK 7 — ns tHCS CSN[0:1] Hold Time to CCLK 1 — ns tSUWD Write Signal Setup Time to CCLK 7 — ns tHWD Write Signal Hold Time to CCLK 1 — ns tDCB CCLK to BUSY Delay Time — 12 ns tCORD CCLK to Out for Read Data — 12 ns sysCONFIG Byte Slave Clocking tBSCH Byte Slave CCLK Minimum High Pulse 6 — ns tBSCL Byte Slave CCLK Minimum Low Pulse 9 — ns tBSCYC Byte Slave CCLK Cycle Time 15 — ns sysCONFIG Serial (Bit) Data Flow tSUSCDI DI Setup Time to CCLK Slave Mode 7 — ns tHSCDI DI Hold Time to CCLK Slave Mode 1 — ns tCODO CCLK to DOUT in Flowthrough Mode — 12 ns sysCONFIG Serial Slave Clocking tSSCH Serial Slave CCLK Minimum High Pulse 6 — ns tSSCL Serial Slave CCLK Minimum Low Pulse 6 — ns sysCONFIG POR, Initialization and Wake-up tICFG Minimum Vcc to INITN High — 28 ms tVMC Time from tICFG to Valid Master CCLK — 2 us tPRGMRJ PROGRAMN Pin Pulse Rejection — 8 ns tPRGM PROGRAMN Low Time to Start Configuration 25 — ns tDINIT PROGRAMN High to INITN High Delay — 1 ms tDPPINIT Delay Time from PROGRAMN Low to INITN Low — 37 ns tDPPDONE Delay Time from PROGRAMN Low to DONE Low — 37 ns tIODISS User I/O Disable from PROGRAMN Low — 35 ns tIOENSS User I/O Enabled Time from CCLK Edge During Wake-up Sequence — 25 ns tMWC Additional Wake Master Clock Signals after DONE Pin High 120 — cycles sysCONFIG SPI Port tCFGX INITN High to CCLK Low — 1 µs tCSSPI INITN High to CSSPIN Low — 2 us tCSCCLK CCLK Low before CSSPIN Low 0 — ns tSOCDO CCLK Low to Output Valid — 15 ns tSOE CSSPIN[0:1] Active Setup Time 300 — ns tCSPID CSSPIN[0:1] Low to First CCLK Edge Setup Time 300+3cyc 600+6cyc ns fMAXSPI Max. CCLK Frequency - SPI Flash Read Opcode (0x03) (SPIFASTN = 1) — 20 MHz Max. CCLK Frequency - SPI Flash Fast Read Opcode (0x0B) (SPIFASTN = 0) — 50 MHz |
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