ECP2 datasheet(12/386 Pages) LATTICE

12 / 386 page

2-9

Architecture

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

Table 2-5. DLL Signals

DLLDELA Delay Block

Closely associated with each DLL is a DLLDELA block. This is a delay block consisting of a delay line with taps and

a selection scheme that selects one of the taps. The DCNTL[8:0] bus controls the delay of the CLKO signal. Typi-

cally this is the delay setting that the DLL uses to achieve phase alignment. This results in the delay providing a cal-

ibrated 90° phase shift that is useful in centering a clock in the middle of a data cycle for source synchronous data.

The CLKO signal feeds the edge clock network. Figure 2-7 shows the connections between the DLL block and the

DLLDELA delay block. For more information, please see the list of additional technical documentation at the end of

this data sheet.

Figure 2-7. DLLDELA Delay Block

PLL/DLL Cascading

LatticeECP2/M devices have been designed to allow certain combinations of PLL (GPLL and SPLL) and DLL cas-

cading. The allowable combinations are:

• PLL to PLL supported

• PLL to DLL supported

Signal

I/O

Description

CLKI

Clock input from external pin or routing

CLKFB

DLL feed input from DLL output, clock net, routing or external pin

RSTN

Active low synchronous reset

ALUHOLD

Active high freezes the ALU

UDDCNTL

Synchronous enable signal (hold high for two cycles) from routing

DCNTL[8:0]

Encoded digital control signals for PIC INDEL and slave delay calibration

CLKOP

The primary clock output

CLKOS

The secondary clock output with ﬁne phase shift and/or division by 2 or by 4

LOCK

Active high phase lock indicator

DLL Block

CLKOP

CLKOS

LOCK

CLKO

CLKI

CLKFB

CLKI

DLLDELA Delay Block

PLL_PIO

DLL_PIO

Routing

CLKFB_CK

ECLK1

CLKOP

GDLLFB_PIO

DCNTL[8:0]

* Software selectable

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