ECP2 datasheet(50/386 Pages) LATTICE

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Architecture

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

Each Transmit and Receive channel has its independent power supplies. The Output and Input buffers of each

channel also have their own independent power supplies. In addition, there are separate power supplies for PLL,

terminating resistor per quad.

Figure 2-40. Simpliﬁed Channel Block Diagram for SERDES and PCS

PCS

As shown in Figure 2-40, the PCS receives the parallel digital data from the deserializer receivers and adjusts the

polarity, detects, byte boundary, decodes (8b/10b) and provides Clock Tolerance Compensation (CTC) FIFO for

changing the clock domain from receiver clock to the FPGA Clock.

For the transmit channel, the PCS block receives the parallel data from the FPGA core, encodes it with 8b/10b,

adjusts the polarity and passes the 8/10 bit data to the transmit SERDES channel.

The PCS also provides bypass modes that allow a direct 8-bit or 10-bit interface from the SERDES to the FPGA

logic. The PCS interface to FPGA can also be programmed to run at 1/2 speed for a 16-bit or 20-bit interface to the

FPGA logic.

SCI (SERDES Client Interface) Bus

The SERDES Client Interface (SCI) is a soft IP interface that allow the SERDES/PCS Quad block to be controlled

by registers as opposed to the conﬁguration memory cells. It is a simple register conﬁguration interface.

The ispLEVER design tools from Lattice support all modes of the PCS. Most modes are dedicated to applications

associated with a speciﬁc industry standard data protocol. Other more general purpose modes allow users to

deﬁne their own operation. With ispLEVER, the user can deﬁne the mode for each quad in a design.

Popular standards such as 10Gb Ethernet and x4 PCI-Express and 4x Serial RapidIO can be implemented using

IP (provided by Lattice), a single quad (Four SERDES channels and PCS) and some additional logic from the core.

For further information about SERDES, please see the list of additional technical documentation at the end of this

data sheet.

Deserializer

1:8/1:10

Polarity

Adjust

Equalizer

Byte Boundary

Detect, 8b/10b

Decoder

CTC

FIFO

Down

Sample

FIFO

Sample

FIFO

8b/10b

Encoder

Polarity

Adjust

Serializer

TX PLL

FPGA Transmit Clock

Recovered Clock

RX REFCLK

FPGA Receive Clock

To FPGA Core

Transmit

Receiver

8/10 bits or

16/20 bits

Transmit Data

Elastic Buffer

Read Clock

16/20 bits

Receive Data

From Transmit PLL

(In Common Block)

SERDES (Analog)

PCS (Digital)

8:1/10:1

TX REFCLK

ECP2 Datasheet(PDF) 50 Page - Lattice Semiconductor

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