ECP2 datasheet(61/386 Pages) LATTICE

61 / 386 page

3-9

DC and Switching Characteristics

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

sysI/O Recommended Operating Conditions

Standard

VCCIO

VREF (V)

Min.

Typ.

Max.

Min.

Typ.

Max.

LVCMOS 3.3

3.135

3.3

3.465

—

LVCMOS 2.5

2.375

2.5

2.625

—

LVCMOS 1.8

1.71

1.8

1.89

—

LVCMOS 1.5

1.425

1.5

1.575

—

LVCMOS 1.2

1.14

1.2

1.26

—

LVTTL

3.135

3.3

3.465

—

PCI

3.135

3.3

3.465

—

SSTL18

2 Class I, II

1.71

1.8

1.89

0.833

0.9

0.969

SSTL2

2 Class I, II

2.375

2.5

2.625

1.15

1.25

1.35

SSTL3

2 Class I, II

3.135

3.3

3.465

1.3

1.5

1.7

HSTL

2 15 Class I

1.425

1.5

1.575

0.68

0.75

0.9

HSTL

2 18 Class I, II

1.71

1.8

1.89

0.816

0.9

1.08

LVDS

2.375

2.5

2.625

—

MLVDS25

2.375

2.5

2.625

—

LVPECL33

1, 2

3.135

3.3

3.465

—

BLVDS25

1, 2

2.375

2.5

2.625

—

RSDS

1, 2

2.375

2.5

2.625

—

SSTL18D_I

2, II2

1.71

1.8

1.89

—

SSTL25D_ I

2, II2

2.375

2.5

2.625

—

SSTL33D_ I

2, II2

3.135

3.3

3.465

—

HSTL15D_ I

1.425

1.5

1.575

—

HSTL18D_ I

2, II2

1.71

1.8

1.89

—

1. Inputs on chip. Outputs are implemented with the addition of external resistors.

2. Input on this standard does not depend on the value of VCCIO.

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