ECP2 datasheet(48/386 Pages) LATTICE

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Architecture

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

Table 2-14. Supported Output Standards

Hot Socketing

LatticeECP2/M devices have been carefully designed to ensure predictable behavior during power-up and power-

down. During power-up and power-down sequences, the I/Os remain in tri-state until the power supply voltage is

high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within speciﬁed limits. This

allows for easy integration with the rest of the system. These capabilities make the LatticeECP2/M ideal for many

multiple power supply and hot-swap applications.

Output Standard

Drive

VCCIO (Nom.)

Single-ended Interfaces

LVTTL

4mA, 8mA, 12mA, 16mA, 20mA

3.3

LVCMOS33

4mA, 8mA, 12mA 16mA, 20mA

3.3

LVCMOS25

4mA, 8mA, 12mA, 16mA, 20mA

2.5

LVCMOS18

4mA, 8mA, 12mA, 16mA

1.8

LVCMOS15

4mA, 8mA

1.5

LVCMOS12

2mA, 6mA

1.2

LVCMOS33, Open Drain

4mA, 8mA, 12mA 16mA, 20mA

—

LVCMOS25, Open Drain

4mA, 8mA, 12mA 16mA, 20mA

—

LVCMOS18, Open Drain

4mA, 8mA, 12mA 16mA

—

LVCMOS15, Open Drain

4mA, 8mA

—

LVCMOS12, Open Drain

2mA, 6mA

—

PCI33

N/A

3.3

HSTL18 Class I, II

N/A

1.8

HSTL15 Class I

N/A

1.5

SSTL3 Class I, II

N/A

3.3

SSTL2 Class I, II

N/A

2.5

SSTL18 Class I, II

N/A

1.8

Differential Interfaces

Differential SSTL3, Class I, II

N/A

3.3

Differential SSTL2, Class I, II

N/A

2.5

Differential SSTL18, Class I, II

N/A

1.8

Differential HSTL18, Class I, II

N/A

1.8

Differential HSTL15, Class I

N/A

1.5

LVDS

N/A

2.5

MLVDS

N/A

2.5

BLVDS

N/A

2.5

LVPECL

N/A

3.3

RSDS

N/A

2.5

LVCMOS33D

4mA, 8mA, 12mA, 16mA, 20mA

3.3

1. Emulated with external resistors. For more detail, please see information regarding additional technical documentation at

the end of this data sheet.

ECP2 Datasheet(PDF) 48 Page - Lattice Semiconductor

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