ECP2 datasheet(101/386 Pages) LATTICE

101 / 386 page

3-49

DC and Switching Characteristics

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

Switching Test Conditions

Figure 3-23 shows the output test load that is used for AC testing. The speciﬁc values for resistance, capacitance,

voltage, and other test conditions are shown in Table 3-18.

Figure 3-22. Output Test Load, LVTTL and LVCMOS Standards

Table 3-18. Test Fixture Required Components, Non-Terminated Interfaces

Test Condition

Timing Ref.

LVTTL and other LVCMOS settings (L -> H, H -> L)

∞∞

0pF

LVCMOS 3.3 = 1.5V

—

LVCMOS 2.5 = VCCIO/2

—

LVCMOS 1.8 = VCCIO/2

—

LVCMOS 1.5 = VCCIO/2

—

LVCMOS 1.2 = VCCIO/2

—

LVCMOS 2.5 I/O (Z -> H)

∞

1MΩ

VCCIO/2

—

LVCMOS 2.5 I/O (Z -> L)

1MΩ

∞

VCCIO/2

VCCIO

LVCMOS 2.5 I/O (H -> Z)

∞

100

VOH - 0.10

—

LVCMOS 2.5 I/O (L -> Z)

100

∞

VOL + 0.10

VCCIO

Note: Output test conditions for all other interfaces are determined by the respective standards.

DUT

CL*

Test Poi nt

*CL Includes Test Fixture and Probe Capacitance

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