ECP2 datasheet(103/386 Pages) LATTICE

103 / 386 page

4-2

Pinout Information

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

[LOC]DQS[num]

I/O

DQ input/output pads: T (top), R (right), B (bottom), L (left), DQS, num = ball

function number.

[LOC]DQ[num]

I/O

DQ input/output pads: T (top), R (right), B (bottom), L (left), DQ, associated

DQS number.

Test and Programming (Dedicated Pins)

TMS

Test Mode Select input, used to control the 1149.1 state machine. Pull-up is

enabled during conﬁguration.

TCK

Test Clock input pin, used to clock the 1149.1 state machine. No pull-up

enabled.

TDI

Test Data in pin. Used to load data into device using 1149.1 state machine.

After power-up, this TAP port can be activated for conﬁguration by sending

appropriate command. (Note: once a conﬁguration port is selected it is

locked. Another conﬁguration port cannot be selected until the power-up

sequence). Pull-up is enabled during conﬁguration.

TDO

Output pin. Test Data Out pin used to shift data out of a device using 1149.1.

VCCJ

—

Power supply pin for JTAG Test Access Port.

Conﬁguration Pads (Used During sysCONFIG)

CFG[2:0]

Mode pins used to specify conﬁguration mode values latched on rising edge

of INITN. During conﬁguration, a pull-up is enabled. These are dedicated

pins.

INITN

I/O

Open Drain pin. Indicates the FPGA is ready to be conﬁgured. During conﬁg-

uration, a pull-up is enabled. It is a dedicated pin.

PROGRAMN

Initiates conﬁguration sequence when asserted low. This pin always has an

active pull-up. This is a dedicated pin.

DONE

I/O

Open Drain pin. Indicates that the conﬁguration sequence is complete, and

the startup sequence is in progress. This is a dedicated pin.

CCLK

I/O

Conﬁguration Clock for conﬁguring an FPGA in sysCONFIG mode.

BUSY/SISPI

I/O

Read control command in SPI or SPIm mode.

CSN

sysCONFIG chip select (active low). During conﬁguration, a pull-up is

enabled.

CS1N

sysCONFIG chip select (active low). During conﬁguration, a pull-up is

enabled.

WRITEN

Write Data on Parallel port (active low).

D[0]/SPIFASTN

I/O

sysCONFIG Port Data I/O for Parallel mode.

sysCONFIG Port Data I/O for SPI or SPIm. When using the SPI or SPIm

mode, this pin should either be tied high or low, must not be left ﬂoating.

D[1:6]

I/O

sysCONFIG Port Data I/O for Parallel

D[7]/SPID0

I/O

sysCONFIG Port Data I/O for Parallel, SPI, SPIm

DOUT/CSON

Output for serial conﬁguration data (rising edge of CCLK) when using

sysCONFIG port.

DI/CSSPI0N

I/O

Input for serial conﬁguration data (clocked with CCLK) when using sysCON-

FIG port. During conﬁguration, a pull-up is enabled. Output when used in SPI/

SPIm modes.

Dedicated SERDES Signals

1, 2, 3

[LOC]_SQ_VCCAUX33

—

Termination resistor switching power (3.3V). This pin must be tied to 3.3V

even if the quad is unused.

[LOC]_SQ_REFCLKN

Negative Reference Clock Input

[LOC]_SQ_REFCLKP

Positive Reference Clock Input

[LOC]_SQ_VCCP

—

PLL and Reference clock buffer power (1.2V). This pin must be tied to 1.2V

even if the quad is unused.

Signal Descriptions (Cont.)

Signal Name

I/O

Description

ECP2 Datasheet(PDF) 103 Page - Lattice Semiconductor

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