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ECP2 Datasheet(PDF) 107 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 107 Page - Lattice Semiconductor |
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107 / 386 page  4-6 Pinout Information Lattice Semiconductor LatticeECP2/M Family Data Sheet Available DDR-Interfaces per I/O Bank 1 Bank0 000000 Bank1 000000 Bank2 010011 Bank3 000000 Bank4 020023 Bank5 010013 Bank6 010011 Bank7 010011 Bank8 000000 PCI Capable I/Os per Bank Bank0 000000 Bank1 000000 Bank2 000000 Bank3 000000 Bank4 18 32 18 19 32 46 Bank5 8 14 10 18 17 46 Bank6 000000 Bank7 000000 Bank8 000000 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + 1 DM + Bank VREF1). LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12 (Cont.) Pin Type LFE2-6 LFE2-12 144 TQFP 256 fpBGA 144 TQFP 208 PQFP 256 fpBGA 484 fpBGA |
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