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ECP2 Datasheet(PDF) 111 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 111 Page - Lattice Semiconductor |
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111 / 386 page  4-10 Pinout Information Lattice Semiconductor LatticeECP2/M Family Data Sheet Available DDR-Interfaces per I/O Bank 1 Bank0 0000 Bank1 0000 Bank2 2334 Bank3 0333 Bank4 3444 Bank5 3445 Bank6 1444 Bank7 2334 Bank8 0000 PCI Capable I/Os per Bank Bank0 0000 Bank1 0000 Bank2 0000 Bank3 0000 Bank4 46 62 62 72 Bank5 46 68 68 80 Bank6 0000 Bank7 0000 Bank8 0000 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + 1 DM + Bank VREF1). LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 (Cont.) Pin Type LFE2-50 LFE2-70 484 fpBGA 672 fpBGA 672 fpBGA 900 fpBGA |
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