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ECP2 Datasheet(PDF) 109 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 109 Page - Lattice Semiconductor |
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109 / 386 page ![]() 4-8 Pinout Information Lattice Semiconductor LatticeECP2/M Family Data Sheet Available DDR-Interfaces per I/O Bank 1 Bank0 000000 Bank1 000000 Bank2 012223 Bank3 000202 Bank4 023333 Bank5 013434 Bank6 012313 Bank7 012223 Bank8 000000 PCI Capable I/Os per Bank Bank0 000000 Bank1 000000 Bank2 000000 Bank3 000000 Bank4 19 32 46 50 46 54 Bank5 18 17 46 68 46 68 Bank6 000000 Bank7 000000 Bank8 000000 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + 1 DM + Bank VREF1). LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35 (Cont.) Pin Type LFE2-20 LFE2-35 208 PQFP 256 fpBGA 484 fpBGA 672 fpBGA 484 fpBGA 672 fpBGA |
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