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ECP2 Datasheet(PDF) 113 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 113 Page - Lattice Semiconductor |
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113 / 386 page  4-12 Pinout Information Lattice Semiconductor LatticeECP2/M Family Data Sheet Available DDR-Interfaces per I/O Bank 1 Bank0 00000 Bank1 00000 Bank2 01013 Bank3 01012 Bank4 24243 Bank5 12123 Bank6 03012 Bank7 12123 Bank8 00000 PCI Capable I/Os per Bank Bank0 00000 Bank1 00000 Bank2 00000 Bank3 00000 Bank4 32 62 32 62 50 Bank5 20 28 20 28 60 Bank6 16 40 16 39 52 Bank7 28 40 28 40 60 Bank8 00000 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + 1 DM + Bank VREF1). LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35 (Cont.) Pin Type LFE2M20 LFE2M35 256 fpBGA 484 fpBGA 256 fpBGA 484 fpBGA 672 fpBGA |
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