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ECP2 Datasheet(PDF) 115 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 115 Page - Lattice Semiconductor |
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115 / 386 page  4-14 Pinout Information Lattice Semiconductor LatticeECP2/M Family Data Sheet Available DDR-Interfaces per I/O Bank 1 Bank0 0 0 0 0000 Bank1 0 0 0 0000 Bank2 2 4 2 4444 Bank3 2 3 1 3435 Bank4 3 1 3 3333 Bank5 2 3 3 2323 Bank6 1 3 2 3435 Bank7 3 4 3 4445 Bank8 0 0 0 0000 PCI Capable I/Os per Bank Bank0 0 0 0 0000 Bank1 0 0 0 0000 Bank2 0000 72 0 80 Bank3 0000 64 0 80 Bank4 50 24 48 48 40 48 44 Bank5 60 60 50 40 40 40 46 Bank6 52 54 60 62 66 62 82 Bank7 60 60 68 70 74 70 90 Bank8 0 0 0 0000 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + 1 DM + Bank VREF1). LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70 and LFE2M100 (Cont.) Pin Type LFE2M50 LFE2M70 LFE2M100 484 fpBGA 672 fpBGA 900 fpBGA 900 fpBGA 1152 fpBGA 900 fpBGA 1152 fpBGA |
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