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ECP2 Datasheet(PDF) 126 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 126 Page - Lattice Semiconductor |
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126 / 386 page  4-25 Pinout Information Lattice Semiconductor LatticeECP2/M Family Data Sheet 136 PT6B 0 C PT16B 0 C 137 PT6A 0 T PT16A 0 T 138 GND - GND - 139 VCCIO0 0 VCCIO0 0 140 PT4B 0 C PT6B 0 C 141 PT4A 0 T PT6A 0 T 142 VCCAUX - VCCAUX - 143 PT2B 0 VREF2_0 C PT2B 0 VREF2_0 C 144 PT2A 0 VREF1_0 T PT2A 0 VREF1_0 T * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one-to-one connection with a package ball or pin. LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP (Cont.) LFE2-6E/SE LFE2-12E/12SE Pin Number Pin/Pad Function Bank Dual Function Differential Pin/Pad Function Bank Dual Function Differential |
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