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ECP2 Datasheet(PDF) 131 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 131 Page - Lattice Semiconductor |
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131 / 386 page ![]() 4-30 Pinout Information Lattice Semiconductor LatticeECP2/M Family Data Sheet 184 GND - GND - 185 PT28A 0 PCLKT0_0 T PT37A 0 PCLKT0_0 T 186 PT26B 0 C PT36B 0 C 187 PT26A 0 T PT36A 0 T 188 VCC - VCC - 189 PT20B 0 C PT30B 0 C 190 VCCAUX - VCCAUX - 191 PT20A 0 T PT30A 0 T 192 GND - GND - 193 PT18B 0 C PT26B 0 C 194 PT18A 0 T PT26A 0 T 195 VCCIO0 0 VCCIO0 0 196 PT16B 0 C PT20B 0 C 197 PT16A 0 T PT20A 0 T 198 VCC - VCC - 199 PT12B 0 C PT12B 0 C 200 PT12A 0 T PT12A 0 T 201 GND - GND - 202 PT8B 0 C PT8B 0 C 203 PT8A 0 T PT8A 0 T 204 PT6B 0 C PT6B 0 C 205 PT6A 0 T PT6A 0 T 206 VCCIO0 0 VCCIO0 0 207 PT2B 0 VREF2_0 C PT2B 0 VREF2_0 C 208 PT2A 0 VREF1_0 T PT2A 0 VREF1_0 T * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.) LFE2-12E/SE LFE2-20E/SE Pin Number Pin/Pad Function Bank Dual Function Differential Pin/Pad Function Bank Dual Function Differential |
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