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ECP2 Datasheet(PDF) 139 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 139 Page - Lattice Semiconductor |
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139 / 386 page  4-38 Pinout Information Lattice Semiconductor LatticeECP2/M Family Data Sheet R12 GND - GND - R5 GND - GND - T1 GND - GND - T16 GND - GND - * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE LFE2-12E/SE Ball Number Ball/Pad Function Bank Dual Function Differential Ball/Pad Function Bank Dual Function Differential |
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