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ECP2 Datasheet(PDF) 147 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 147 Page - Lattice Semiconductor |
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147 / 386 page ![]() 4-46 Pinout Information Lattice Semiconductor LatticeECP2/M Family Data Sheet P5 P5 VCCIO5 5 K5 K5 VCCIO6 6 M3 M3 VCCIO6 6 E3 E3 VCCIO7 7 G5 G5 VCCIO7 7 T15 T15 VCCIO8 8 A1 A1 GND - A16 A16 GND - B12 B12 GND - B5 B5 GND - C8 C8 GND - E15 E15 GND - E2 E2 GND - H14 H14 GND - H8 H8 GND - H9 H9 GND - J3 J3 GND - J8 J8 GND - J9 J9 GND - M15 M15 GND - M2 M2 GND - P9 P9 GND - R12 R12 GND - R5 R5 GND - T1 T1 GND - T16 T16 GND - * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-20E/SE Ball Number Ball Number Ball/Pad Function Bank Dual Function Differential |
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