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ECP2 Datasheet(PDF) 160 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 160 Page - Lattice Semiconductor |
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160 / 386 page ![]() 4-59 Pinout Information Lattice Semiconductor LatticeECP2/M Family Data Sheet L8 GND - GND - M10 GND - GND - M11 GND - GND - M12 GND - GND - M13 GND - GND - M15 GND - GND - M8 GND - GND - N10 GND - GND - N11 GND - GND - N12 GND - GND - N13 GND - GND - N15 GND - GND - N8 GND - GND - P14 GND - GND - P20 GND - GND - P3 GND - GND - P9 GND - GND - R10 GND - GND - R11 GND - GND - R12 GND - GND - R13 GND - GND - U17 GND - GND - U6 GND - GND - W2 GND - GND - W21 GND - GND - Y14 GND - GND - Y9 GND - GND - H6 NC - NC - J6 NC - NC - H3 NC - NC - H2 NC - NC - H17 NC - NC - H16 NC - NC - H20 NC - NC - H18 NC - NC - K6 NC - NC - J16 NC - NC - N18 VCC - VCC - N6 VCC - VCC - * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE LFE2-20E/20SE Ball Number Ball/Pad Function Bank Dual Function Differential Ball/Pad Function Bank Dual Function Differential |
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