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ECP2 Datasheet(PDF) 234 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 234 Page - Lattice Semiconductor |
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234 / 386 page  4-133 Pinout Information Lattice Semiconductor LatticeECP2/M Family Data Sheet E27 NC - E28 NC - E29 NC - E3 NC - E30 NC - E4 NC - E5 NC - E6 NC - F25 NC - F5 NC - F6 NC - G6 NC - G7 NC - K10 NC - K9 NC - N27 NC - N4 NC - R1 NC - R2 NC - V27 NC - V4 NC - P22 VCCPLL - P8 VCCPLL - T22 VCCPLL - Y7 VCCPLL - * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. ***Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number Ball/Pad Function Bank Dual Function Differential |
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