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ECP2 Datasheet(PDF) 241 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 241 Page - Lattice Semiconductor |
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241 / 386 page ![]() 4-140 Pinout Information Lattice Semiconductor LatticeECP2/M Family Data Sheet H8 GND - GND - H9 GND - GND - J3 GND - GND - J8 GND - GND - J9 GND - GND - M15 GND - GND - M2 GND - GND - P9 GND - GND - R12 GND - GND - R5 GND - GND - T1 GND - GND - T16 GND - GND - D10 NC - NC - D11 NC - NC - D12 NC - NC - D13 NC - NC - D14 NC - NC - D4 NC - NC - D5 NC - NC - D6 NC - NC - D7 NC - NC - E11 NC - NC - E6 NC - NC - E8 NC - NC - E9 NC - NC - F10 NC - NC - F7 NC - NC - F8 NC - NC - F9 NC - NC - * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. ***Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA LFE2M20E/SE LFE2M35E/SE Ball Number Ball/Pad Function Bank Dual Function Differential Ball/Pad Function Bank Dual Function Differential |
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