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ECP2 Datasheet(PDF) 253 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 253 Page - Lattice Semiconductor |
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253 / 386 page ![]() 4-152 Pinout Information Lattice Semiconductor LatticeECP2/M Family Data Sheet K3 GND - GND - K8 GND - GND - L10 GND - GND - L11 GND - GND - L12 GND - GND - L13 GND - GND - M10 GND - GND - M11 GND - GND - M12 GND - GND - M13 GND - GND - N10 GND - GND - N11 GND - GND - N12 GND - GND - N13 GND - GND - N15 GND - GND - N20 GND - GND - N3 GND - GND - N8 GND - GND - P14 GND - GND - P9 GND - GND - R10 GND - GND - R13 GND - GND - T19 GND - GND - T4 GND - GND - W16 GND - GND - W2 GND - GND - W21 GND - GND - W7 GND - GND - Y10 GND - GND - Y13 GND - GND - D15 NC - NC - G14 NC - NC - G15 NC - NC - D14 NC - NC - E15 NC - NC - E14 NC - NC - F15 NC - NC - F14 NC - NC - F13 NC - NC - G12 NC - NC - G13 NC - NC - * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. ***For density migration, board design must take into account that these sysCONFIG pins are dual function for the lower density devices (ECP2M20 and ECP2M35) and are dedicated pins for the higher density devices (ECP2M50, ECP2M70 and ECP2M100). ****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA LFE2M20E/SE LFE2M35E/SE Ball Number Ball/Pad Function Bank Dual Function Differential Ball/Pad Function Bank Dual Function Differential |
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