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ECP2 Datasheet(PDF) 267 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 267 Page - Lattice Semiconductor |
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267 / 386 page ![]() 4-166 Pinout Information Lattice Semiconductor LatticeECP2/M Family Data Sheet W19 NC - W18 NC - V17 NC - V18 NC - D15 NC - G14 NC - G15 NC - D14 NC - E15 NC - E14 NC - F15 NC - F14 NC - F13 NC - G12 NC - G13 NC - H8 VCCPLL - H15 VCCPLL - R8 VCCPLL - R15 VCCPLL - * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. ***For density migration, board design must take into account that these sysCONFIG pins are dual function for the lower density devices (ECP2M20 and ECP2M35) and are dedicated pins for the higher density devices (ECP2M50, ECP2M70 and ECP2M100). ****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.) LFE2M50E/SE Ball Number Ball/Pad Function Bank Dual Function Differential |
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