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ECP2 Datasheet(PDF) 306 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 306 Page - Lattice Semiconductor |
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306 / 386 page ![]() 4-205 Pinout Information Lattice Semiconductor LatticeECP2/M Family Data Sheet J10 PL2B 7 LDQ6 C (LVDS)* NC - J20 NC - NC - J21 NC - NC - J9 PL4A 7 LDQ6 T (LVDS)* NC - K9 PL4B 7 LDQ6 C (LVDS)* NC - R9 NC - NC - U22 NC - NC - W9 NC - NC - N13 VCCPLL - VCCPLL - N18 VCCPLL - VCCPLL - V13 VCCPLL - VCCPLL - V18 VCCPLL - VCCPLL - * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. *** These sysCONFIG pins are dedicated I/O pins for configuration. The outpus are actively driven during normal device operation. ****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one con- nection with a package ball or pin. LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE LFE2M70E/SE Ball Number Ball/Pad Function Bank Dual Function Differential Ball/Pad Function Bank Dual Function Differential |
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