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ECP2 Datasheet(PDF) 331 Page - Lattice Semiconductor |
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ECP2 Datasheet(HTML) 331 Page - Lattice Semiconductor |
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331 / 386 page  4-230 Pinout Information Lattice Semiconductor LatticeECP2/M Family Data Sheet J21 NC - J9 NC - K9 NC - R9 NC - U22 NC - W9NC - N13 VCCPLL - N18 VCCPLL - V13 VCCPLL - V18 VCCPLL - * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. *** These sysCONFIG pins are dedicated I/O pins for configuration. The outpus are actively driven during normal device operation. ****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number Ball/Pad Function Bank Dual Function Differential |
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