7516 datasheet(35/90 Pages) RENESAS

35 / 90 page

Rev.1.01

Jul 01, 2003

page 35 of 89

7516 Group

Fig. 36 START condition detecting timing diagram

START/STOP Condition Detecting Operation

The START/STOP condition detection operations are shown in

Figures 36, 37, and Table 11. The START/STOP condition is set

by the START/STOP condition set bit.

The START/STOP condition can be detected only when the input

signal of the SCL and SDA pins satisfy three conditions: SCL re-

lease time, setup time, and hold time (see Table 11).

The BB flag is set to “1” by detecting the START condition and is

reset to “0” by detecting the STOP condition.

The BB flag set/reset timing is different in the standard clock mode

and the high-speed clock mode. Refer to Table 11, the BB flag set/

reset time.

Note: When a STOP condition is detected in the slave mode (MST = 0), an

interrupt request signal “IICIRQ” occurs to the CPU.

START Condition Generating Method

When writing “1” to the MST, TRX, and BB bits of the I2C status

address to the I2C data shift register (address 002B16) with the

condition in which the ES0 bit of the I2C control register (address

002E16) and the BB flag are “0”, a START condition occurs. After

that, the bit counter becomes “0002” and an SCL for 1 byte is out-

put. The START condition generating timing is different in the

standard clock mode and the high-speed clock mode. Refer to

Figure 34, the START condition generating timing diagram, and

Table 9, the START condition generating timing table.

STOP Condition Generating Method

When the ES0 bit of the I2C control register (address 002E16) is

“1,” write “1” to the MST and TRX bits, and write “0” to the BB bit

of the I2C status register (address 002D16) simultaneously. Then a

STOP condition occurs. The STOP condition generating timing is

different in the standard clock mode and the high-speed clock

mode. Refer to Figure 35, the STOP condition generating timing

diagram, and Table 10, the STOP condition generating timing

table.

Fig. 34 START condition generating timing diagram

Fig. 35 STOP condition generating timing diagram

Table 10 STOP condition generating timing table

Item

Setup time

Hold time

Standard clock mode

5.0

µs (20 cycles)

4.5

µs (18 cycles)

Note: Absolute time at

φ = 4 MHz. The value in parentheses denotes the

number of

φ cycles.

High-speed clock mode

3.0

µs (12 cycles)

2.5

µs (10 cycles)

Table 9 START condition generating timing table

Item

Setup time

Hold time

Standard clock mode

5.0

µs (20 cycles)

5.0

µs (20 cycles)

Note: Absolute time at

φ = 4 MHz. The value in parentheses denotes the

number of

φ cycles.

High-speed clock mode

2.5

µs (10 cycles)

2.5

µs (10 cycles)

Table 11 START condition/STOP condition detecting conditions

Note: Unit : Cycle number of system clock

SSC value is the decimal notation value of the START/STOP condi-

tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC

value. The value in parentheses is an example when the I2C START/

STOP condition control register is set to “1816” at

φ = 4 MHz.

Fig. 37 STOP condition detecting timing diagram

SCL release time

Standard clock mode

High-speed clock mode

4 cycles (1.0

µs)

2 cycles (1.0

µs)

2 cycles (0.5

µs)

3.5 cycles (0.875

µs)

SSC value + 1

SSC value –1

Setup time

Hold time

BB flag set/

reset time

SSC value + 1 cycle (6.25

µs)

cycle < 4.0

µs (3.125 µs)

cycle < 4.0

µs (3.125 µs)

+ 2 cycles (3.375

µs)

I2C status register

write signal

Hold time

Setup

time

SCL

SDA

I2C status register

write signal

Hold time

Setup

time

SCL

SDA

Hold time

Setup

time

SCL

SDA

BB flag

SCL release time

BB flag

reset

time

Hold time

Setup

time

SCL

SDA

BB flag

SCL release time

BB flag

reset

time

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