7516 datasheet(20/90 Pages) RENESAS

20 / 90 page

Rev.1.01

Jul 01, 2003

page 20 of 89

7516 Group

TIMERS

The 7516 group has four timers: timer X, timer Y, timer 1, and

timer 2.

The division ratio of each timer or prescaler is given by 1/(n + 1),

where n is the value in the corresponding timer or prescaler latch.

All timers are count down. When the timer reaches “0016”, an un-

derflow occurs at the next count pulse and the corresponding

timer latch is reloaded into the timer and the count is continued.

When a timer underflows, the interrupt request bit corresponding

to that timer is set to “1”.

Timer X and Timer Y

Timer X and Timer Y can each select in one of four operating

modes by setting the timer XY mode register.

(1) Timer Mode

The timer counts the count source selected by Timer count source

selection bit.

(2) Pulse Output Mode

The timer counts the count source selected by Timer count source

selection bit. Whenever the contents of the timer reach “0016”, the

signal output from the CNTR0 (or CNTR1) pin is inverted. If the

CNTR0 (or CNTR1) active edge selection bit is “0”, output begins

at “ H”.

If it is “1”, output starts at “L”. When using a timer in this mode, set

the corresponding port P27 ( or port P40) direction register to out-

put mode.

(3) Event Counter Mode

Operation in event counter mode is the same as in timer mode,

except that the timer counts signals input through the CNTR0 or

CNTR1 pin.

When the CNTR0 (or CNTR1) active edge selection bit is “0”, the

rising edge of the CNTR0 (or CNTR1) pin is counted.

When the CNTR0 (or CNTR1) active edge selection bit is “1”, the

falling edge of the CNTR0 (or CNTR1) pin is counted.

(4) Pulse Width Measurement Mode

If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer

counts the selected signals by the count source selection bit while

the CNTR0 (or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) ac-

tive edge selection bit is “1”, the timer counts it while the CNTR0

(or CNTR1) pin is at “L”.

The count can be stopped by setting “1” to the timer X (or timer Y)

count stop bit in any mode. The corresponding interrupt request

bit is set each time a timer underflows.

Fig. 15 Structure of timer XY mode register

sNote

When switching the count source by the timer 12, X and Y count

source bits, the value of timer count is altered in unconsiderable

amount owing to generating of a thin pulses in the count input

signals.

Therefore, select the timer count source before set the value to

the prescaler and the timer.

When timer X/timer Y underflow while executing the instruction

which sets “1” to the timer X/timer Y count stop bits, the timer X/

timer Y interrupt request bits are set to “1”. Timer X/Timer Y in-

terrupts are received if these interrupts are enabled at this time.

The timing which interrupt is accepted has a case after the in-

struction which sets “1” to the count stop bit, and a case after

the next instruction according to the timing of the timer under-

flow. When this interrupt is unnecessary, set “0” (disabled) to the

interrupt enable bit and then set “1” to the count stop bit.

Fig. 16 Structure of timer count source selection register

Timer 1 and Timer 2

The count source of prescaler 12 is the oscillation frequency

which is selected by timer 12 count source selection bit. The out-

put of prescaler 12 is counted by timer 1 and timer 2, and a timer

underflow sets the interrupt request bit.

Timer X count stop bit

0: Count start

1: Count stop

Timer XY mode register

(TM : address 002316)

Timer Y operating mode bits

0 0: Timer mode

0 1: Pulse output mode

1 0: Event counter mode

1 1: Pulse width measurement mode

CNTR1 active edge selection bit

0: Interrupt at falling edge

Count at rising edge in event

counter mode

1: Interrupt at rising edge

Count at falling edge in event

counter mode

CNTR0 active edge selection bit

0: Interrupt at falling edge

Count at rising edge in event

counter mode

1: Interrupt at rising edge

Count at falling edge in event

counter mode

Timer X operating mode bits

0 0: Timer mode

0 1: Pulse output mode

1 0: Event counter mode

1 1: Pulse width measurement mode

b1b0

b5b4

Timer Y count stop bit

0: Count start

1: Count stop

Timer count source selection register

(TCSS : address 002816)

Timer X count source selection bit

0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)

1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)

Timer Y count source selection bit

0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)

1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)

Timer 12 count source selection bit

0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)

1 : f(XCIN)

Not used (returns “0” when read)

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