7516 datasheet(76/90 Pages) RENESAS

76 / 90 page

Rev.1.01

Jul 01, 2003

page 76 of 89

7516 Group

NOTES ON PROGRAMMING

Processor Status Register

The contents of the processor status register (PS) after a reset are

undefined, except for the interrupt disable flag (I) which is “1.” Af-

ter a reset, initialize flags which affect program execution. In

particular, it is essential to initialize the index X mode (T) and the

decimal mode (D) flags because of their effect on calculations.

Interrupts

The contents of the interrupt request bits do not change immedi-

ately after they have been written. After writing to an interrupt

request register, execute at least one instruction before perform-

ing a BBC or BBS instruction.

Decimal Calculations

• To calculate in decimal notation, set the decimal mode flag (D)

to “1”, then execute an ADC or SBC instruction. After executing

an ADC or SBC instruction, execute at least one instruction be-

fore executing a SEC, CLC, or CLD instruction.

• In decimal mode, the values of the negative (N), overflow (V),

and zero (Z) flags are invalid.

Timers

If a value n (between 0 and 255) is written to a timer latch, the fre-

quency division ratio is 1/(n+1).

Multiplication and Division Instructions

• The index X mode (T) and the decimal mode (D) flags do not af-

fect the MUL and DIV instruction.

• The execution of these instructions does not change the con-

tents of the processor status register.

Ports

The contents of the port direction registers cannot be read. The

following cannot be used:

• The data transfer instruction (LDA, etc.)

• The operation instruction when the index X mode flag (T) is “1”

• The addressing mode which uses the value of a direction regis-

ter as an index

• The bit-test instruction (BBC or BBS, etc.) to a direction register

• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to

a direction register.

Use instructions such as LDM and STA, etc., to set the port direc-

tion registers.

Serial I/O

In serial I/O1 (clock synchronous mode), if the receive side is us-

ing an external clock and it is to output the SRDY1 signal, set the

transmit enable bit, the receive enable bit, and the SRDY1 output

enable bit to “1.”

Serial I/O1 continues to output the final bit from the TXD pin after

transmission is completed.

SOUT2 pin for serial I/O2 goes to high impedance after transmis-

sion is completed.

When an external clock is used as synchronous clock in serial

I/O1 or serial I/O2, write transmission data to the transmit buffer

A-D Converter

The comparator uses capacitive coupling amplifier whose charge

will be lost if the clock frequency is too low.

Therefore, make sure that f(XIN) in the middle/high-speed mode is

at least on 500 kHz during an A-D conversion.

Do not execute the STP instruction or the WIT instruction during

an A-D conversion.

Instruction Execution Time

The instruction execution time is obtained by multiplying the fre-

quency of the internal clock

φ by the number of cycles needed to

execute an instruction.

The number of cycles required to execute an instruction is shown

in the list of machine instructions.

The frequency of the internal clock

φ is half of the XIN frequency in

high-speed mode.

NOTES ON USAGE

Handling of Source Pins

In order to avoid a latch-up occurrence, connect a capacitor suit-

able for high frequencies as bypass capacitor between power

source pin (VCC pin) and GND pin (VSS pin) and between power

source pin (VCC pin) and analog power source input pin (AVSS

pin). Besides, connect the capacitor to as close as possible. For

bypass capacitor which should not be located too far from the pins

to be connected, a ceramic capacitor of 0.01

µF–0.1µF is recom-

mended.

EPROM Version/One Time PROM Version/

Flash Memory Version

The CNVss pin is connected to the internal memory circuit block

by a low-ohmic resistance, since it has the multiplexed function to

be a programmable power source pin (VPP pin) as well.

To improve the noise reduction, connect a track between CNVss

pin and Vss pin or Vcc pin with 1 to 10 k

Ω resistance.

The mask ROM version track of CNVss pin has no operational in-

terference even if it is connected to Vss pin or Vcc pin via a

resistor.

Electric Characteristic Differences Among

Mask ROM, Flash Memory, and One Time

PROM Version MCUs

There are differences in electric characteristics, operation margin,

noise immunity, and noise radiation among mask ROM, flash

memory, and One Time PROM version MCUs due to the differ-

ences in the manufacturing processes.

When manufacturing an application system with the flash memory,

One Time PROM version and then switching to use of the mask

ROM version, perform sufficient evaluations for the commercial

samples of the mask ROM version.

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