7516 datasheet(84/90 Pages) RENESAS

84 / 90 page

Rev.1.01

Jul 01, 2003

page 84 of 89

7516 Group

Table 31 Switching characteristics 1

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Serial I/O1 clock output “H” pulse width

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time (Note 2)

Serial I/O2 output valid time (Note 2)

Serial I/O2 clock output falling time

CMOS output rising time (Note 3)

CMOS output falling time (Note 3)

tWH (SCLK1)

tWL (SCLK1)

td (SCLK1-TXD)

tv (SCLK1-TXD)

tr (SCLK1)

tf (SCLK1)

tWH (SCLK2)

tWL (SCLK2)

td (SCLK2-SOUT2)

tv (SCLK2-SOUT2)

tf (SCLK2)

tr (CMOS)

tf (CMOS)

Limits

Parameter

Min.

tC(SCLK1)/2–30

–30

tC(SCLK2)/2–160

Typ.

Max.

140

200

Symbol

Unit

Notes 1: For tWH(SCLK1), tWL(SCLK1), when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register (bit 7 of address 001516) is “0”.

3: The XOUT pin is excluded.

Table 32 Switching characteristics 2

(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)