7516 datasheet(42/90 Pages) RENESAS

42 / 90 page

Rev.1.01

Jul 01, 2003

page 42 of 89

7516 Group

A-D CONVERTER

[A-D Conversion Registers (ADL, ADH)]

003516, 003616

The A-D conversion registers are read-only registers that store the

result of an A-D conversion. Do not read these registers during an

A-D conversion

[AD Control Register (ADCON)] 003416

The AD control register controls the A-D conversion process. Bits

0 to 2 select a specific analog input pin. Bit 4 indicates the

completion of an A-D conversion. The value of this bit remains at

“0” during an A-D conversion and changes to “1” when an A-D

conversion ends. Writing “0” to this bit starts the A-D conversion.

Comparison Voltage Generator

The comparison voltage generator divides the voltage between

AVSS and VREF into 1024 and outputs the divided voltages.

Channel Selector

The channel selector selects one of ports P30/AN0 to P37/AN7 and

inputs the voltage to the comparator.

Comparator and Control Circuit

The comparator and control circuit compare an analog input volt-

age with the comparison voltage, and the result is stored in the

A-D conversion registers. When an A-D conversion is completed,

the control circuit sets the A-D conversion completion bit and the

A-D interrupt request bit to “1”.

Note that because the comparator consists of a capacitor cou-

pling, set f(XIN) to 500 kHz or more during an A-D conversion.

When the A-D converter is operated at low-speed mode, f(XIN)

and f(XCIN) do not have the lower limit of frequency, because of

the A-D converter has a built-in self-oscillation circuit.

Fig. 44 Structure of AD control register

Fig. 45 Structure of A-D conversion registers

Fig. 46 Block diagram of A-D converter

AD control register

(ADCON : address 003416)

Analog input pin selection bits

b2 b1 b0

0 0 0: P30/AN0

0 0 1: P31/AN1

0 1 0: P32/AN2

0 1 1: P33/AN3

1 0 0: P34/AN4

1 0 1: P35/AN5

1 1 0: P36/AN6

1 1 1: P37/AN7

Not used (returns “0” when read)

A-D conversion completion bit

0: Conversion in progress

1: Conversion completed

Not used (returns “0” when read)

10-bit reading

(Read address 003616 before 003516)

(Address 003616)

(Address 003516)

8-bit reading (Read only address 003516)

(Address 003516)

b7 b6 b5 b4 b3 b2 b1 b0

Note : The high-order 6 bits of address 003616 become “0”

at reading.

b9 b8 b7 b6 b5 b4 b3 b2

A-D control circuit

A-D conversion low-order register

Resistor ladder

VREF AVSS

Comparator

A-D interrupt request

P30/AN0

P31/AN1

P32/AN2

P33/AN3

P34/AN4

Data bus

AD control register

A-D conversion high-order register

(Address 003416)

(Address 003616)

(Address 003516)

P35/AN5

P36/AN6

P37/AN7

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