HD64F36079G datasheet(78/564 Pages) RENESAS

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Section 3 Exception Handling

Rev. 3.00 Sep. 10, 2007 Page 46 of 528

REJ09B0216-0300

3.1

Exception Sources and Vector Address

Table 3.1 shows the vector addresses and priority of each exception handling. When more than

one interrupt is requested, handling is performed from the interrupt with the highest priority.

Table 3.1

Exception Sources and Vector Address

Relative Module

Exception Sources

Vector

Number

Normal Mode

Advanced Mode

Priority

RES pin

Watchdog timer

Reset

H'0000 to H'0001

H'000000 to H'000003

High



Reserved for system use 1 to 6

H'0002 to H'000D H'000004 to H'00001B

External interrupt

NMI

H'000E to H'000F H'00001C to H'00001F

CPU

Trap instruction #0

H'0010 to H'0011

H'000020 to H'000023

Trap instruction #1

H'0012 to H'0013

H'000024 to H'000027

Trap instruction #2

H'0014 to H'0015

H'000028 to H'00002B

Trap instruction #3

H'0016 to H'0017

H'00002C to H'00002F

Address break

Break conditions satisfied 12

H'0018 to H'0019

H'000030 to H'000033

CPU

Direct transition by

executing the SLEEP

instruction

H'001A to H'001B H'000034 to H'000037

External interrupt

IRQ0

Low-voltage detection

interrupt

H'001C to H'001D H'000038 to H'00003B

IRQ1

H'001E to H'001F H'00003C to H'00003F

IRQ2

H'0020 to H'0021

H'000040 to H'000043

IRQ3

H'0022 to H'0023

H'000044 to H'000047

WKP

H'0024 to H'0025

H'000048 to H'00004B

RTC

Overflow

H'0026 to H'0027

H'00004C to H'0004F

Low

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