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HD64F36079G Datasheet(PDF) 22 Page - Renesas Technology Corp |
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HD64F36079G Datasheet(HTML) 22 Page - Renesas Technology Corp |
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22 / 564 page  Rev. 3.00 Sep. 10, 2007 Page xxii of xxxii Figure 5.5 Flowchart of Clock Switching with Backup Function Disabled (2) (From External Clock to On-Chip Oscillator Clock).................................................. 82 Figure 5.6 Timing Chart of Switching from On-Chip Oscillator Clock to External Clock............................................................................................................ 83 Figure 5.7 Timing Chart to Switch from External Clock to On-Chip Oscillator Clock .......................................................................................................... 84 Figure 5.8 External Oscillation Backup Timing ........................................................................... 85 Figure 5.9 Example of Trimming Flow for On-Chip Oscillator Clock ........................................ 86 Figure 5.10 Timing Chart of Trimming of On-Chip Oscillator Frequency .................................. 87 Figure 5.11 Block Diagram of External Clock Oscillator ............................................................ 88 Figure 5.12 Example of Connection to Crystal Resonator ........................................................... 88 Figure 5.13 Equivalent Circuit of Crystal Resonator.................................................................... 89 Figure 5.14 Example of Connection to Ceramic Resonator ......................................................... 89 Figure 5.15 Example of External Clock Input .............................................................................. 89 Figure 5.16 Block Diagram of Subclock Oscillator...................................................................... 90 Figure 5.17 Typical Connection to 32.768-kHz Crystal Resonator.............................................. 90 Figure 5.18 Equivalent Circuit of 32.768-kHz Crystal Resonator................................................ 90 Figure 5.19 Pin Connection when not Using Subclock ................................................................ 91 Figure 5.20 Example of Incorrect Board Design .......................................................................... 92 Section 6 Power-Down Modes Figure 6.1 Mode Transition Diagram ......................................................................................... 100 Section 7 ROM Figure 7.1 Flash Memory Block Configuration (1) (H8/36079GF and H8/36079LF) ............... 108 Figure 7.1 Flash Memory Block Configuration (2) (H8/36078GF and H8/36078LF) ............... 109 Figure 7.1 Flash Memory Block Configuration (3) (H8/36077GF and H8/36077LF) ............... 110 Figure 7.1 Flash Memory Block Configuration (4) (H8/36074GF and H8/36074LF) ............... 111 Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode.......................... 120 Figure 7.3 Program/Program-Verify Flowchart ......................................................................... 122 Figure 7.4 Erase/Erase-Verify Flowchart ................................................................................... 125 Section 9 I/O Ports Figure 9.1 Port 1 Pin Configuration............................................................................................ 131 Figure 9.2 Port 2 Pin Configuration............................................................................................ 137 Figure 9.3 Port 3 Pin Configuration............................................................................................ 141 Figure 9.4 Port 5 Pin Configuration............................................................................................ 145 Figure 9.5 Port 6 Pin Configuration............................................................................................ 151 Figure 9.6 Port 7 Pin Configuration............................................................................................ 156 Figure 9.7 Port 8 Pin Configuration............................................................................................ 159 Figure 9.8 Port B Pin Configuration........................................................................................... 161 Figure 9.9 Port C Pin Configuration........................................................................................... 165 |
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