HD64F36079G datasheet(93/564 Pages) RENESAS

93 / 564 page

Section 3 Exception Handling

Rev. 3.00 Sep. 10, 2007 Page 61 of 528

REJ09B0216-0300

Interrupt

request signal

Normal mode operation

Advanced mode operation

Internal

address bus

Internal

read signal

Internal

write signal

Internal data

bus (16 bits)

Interrupt level

decision and wait

for end of instruction

Prefetch instruction of

interrupt handling routine

Interrupt is accepted

Instruction

prefetch

Stack access

Vector fetch

Internal

processing

Internal

processing

(1)

(2)

(4)

(1)

(7)

(9)

(10)

(3)

(5)

(6)

(8)

(9)

(1)

Instruction prefetch address (Instruction is not executed.

Address is saved as PC contents, becoming return address.)

(2), (4) Instruction code (Instruction is not executed.)

(3)

Instruction prefetch address (Instruction is not executed.)

(5)

SP - 2

(6)

SP - 4

(7)

CCR

(8)

Vector address

(9)

Start address of interrupt handling routine (contents of vector)

(10)

First instruction of interrupt handling routine.

(14)

(12)

(6)

(4)

High level

(2)

(1)

(5)

(7)

(9)

(11)

(13)

Prefetch instruction of

interrupt handling routine

Internal

processing

Vector fetch

Stack access

Instruction

prefetch

Internal

processing

Interrupt level

decision and wait

for end of instruction

Interrupt is accepted

Interrupt

request signal

Internal

address bus

Internal

read signal

Internal

write signal

Internal

data bus

(3)

(1)

Instruction prefetch address (Instruction is not executed.

Address is saved as PC contents, becoming return address.)

(2), (4) Instruction code (Instruction is not executed.)

(3)

Instruction prefetch address (Instruction is not executed.)

(5)

SP - 2

(7)

SP - 4

(6), (8)

Saved PC and CCR

(9), (11)

Vector address

(10), (12) Start address of interrupt handling routine (contents of vector)

(13)

Start address of interrupt handling routine ((13), (10), (12))

(14)

First instruction of interrupt handling routine.

(8)

(10)

Figure 3.3 Interrupt Sequence

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