HD64F36079G datasheet(88/564 Pages) RENESAS

88 / 564 page

Section 3 Exception Handling

Rev. 3.00 Sep. 10, 2007 Page 56 of 528

REJ09B0216-0300

3.4

Interrupt Exception Handling

3.4.1

External Interrupts

As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts.

(1)

NMI Interrupt

NMI interrupt is requested by input signal edge to pin

NMI. This interrupt is detected by either

rising edge sensing or falling edge sensing, depending on the setting of bit NMIEG in IEGR1.

NMI is the highest-priority interrupt, and can always be accepted without depending on the I

bit value in CCR.

(2)

IRQ3 to IRQ0 Interrupts

IRQ3 to IRQ0 interrupts are requested by input signals to pins

IRQ3 to IRQ0. These four

interrupts are given different vector addresses, and are detected individually by either rising

edge sensing or falling edge sensing, depending on the settings of bits IEG3 to IEG0 in IEGR1.

When pins

IRQ3 to IRQ0 are designated for interrupt input in PMR1 and the designated signal

edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt.

These interrupts can be masked by setting bits IEN3 to IEN0 in IENR1.

(3)

WKP5 to WKP0 Interrupts

WKP5 to WKP0 interrupts are requested by input signals to pins

WKP5 to WKP0. These six

interrupts have the same vector addresses, and are detected individually by either rising edge

sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in

IEGR2.

When pins

WKP5 to WKP0 are designated for interrupt input in PMR5 and the designated

signal edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an

interrupt. These interrupts can be masked by setting bit IENWP in IENR1.

HD64F36079G Datasheet(PDF) 88 Page - Renesas Technology Corp