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HD64F36079G Datasheet(PDF) 16 Page - Renesas Technology Corp

Part # HD64F36079G
Description  Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series
PDF  564 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F36079G Datasheet(HTML) 16 Page - Renesas Technology Corp

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Rev. 3.00 Sep. 10, 2007 Page xvi of xxxii
16.4.3
Data Transmission ............................................................................................ 305
16.4.4
Serial Data Reception ....................................................................................... 307
16.5
Operation in Clock Synchronous Mode............................................................................ 311
16.5.1
Clock................................................................................................................. 311
16.5.2
SCI3 Initialization............................................................................................. 311
16.5.3
Serial Data Transmission .................................................................................. 312
16.5.4
Serial Data Reception (Clock Synchronous Mode) .......................................... 314
16.5.5
Simultaneous Serial Data Transmission and Reception.................................... 316
16.6
Multiprocessor Communication Function ........................................................................ 318
16.6.1
Multiprocessor Serial Data Transmission ......................................................... 319
16.6.2
Multiprocessor Serial Data Reception .............................................................. 321
16.7
Interrupts........................................................................................................................... 325
16.8
Usage Notes ...................................................................................................................... 326
16.8.1
Break Detection and Processing ....................................................................... 326
16.8.2
Mark State and Break Sending ......................................................................... 326
16.8.3
Receive Error Flags and Transmit Operations
(Clock Synchronous Mode Only) ..................................................................... 326
16.8.4
Receive Data Sampling Timing and Reception Margin in
Asynchronous Mode......................................................................................... 327
Section 17 I
2C Bus Interface 2 (IIC2)..................................................................329
17.1
Features............................................................................................................................. 329
17.2
Input/Output Pins.............................................................................................................. 331
17.3
Register Descriptions ........................................................................................................ 332
17.3.1
I
2C Bus Control Register 1 (ICCR1)................................................................. 332
17.3.2
I
2C Bus Control Register 2 (ICCR2)................................................................. 335
17.3.3
I
2C Bus Mode Register (ICMR)........................................................................ 336
17.3.4
I
2C Bus Interrupt Enable Register (ICIER) ....................................................... 338
17.3.5
I
2C Bus Status Register (ICSR)......................................................................... 340
17.3.6
Slave Address Register (SAR).......................................................................... 343
17.3.7
I
2C Bus Transmit Data Register (ICDRT)......................................................... 344
17.3.8
I
2C Bus Receive Data Register (ICDRR).......................................................... 344
17.3.9
I
2C Bus Shift Register (ICDRS)........................................................................ 344
17.4
Operation .......................................................................................................................... 345
17.4.1
I
2C Bus Format.................................................................................................. 345
17.4.2
Master Transmit Operation ............................................................................... 346
17.4.3
Master Receive Operation................................................................................. 348
17.4.4
Slave Transmit Operation ................................................................................. 350
17.4.5
Slave Receive Operation................................................................................... 352
17.4.6
Clock Synchronous Serial Format .................................................................... 354



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