HD64F36079G datasheet(103/564 Pages) RENESAS

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Section 5 Clock Pulse Generator

CPG0200A_000020020200

Rev. 3.00 Sep. 10, 2007 Page 71 of 528

REJ09B0216-0300

Section 5 Clock Pulse Generator

The clock pulse generator (CPG) consists of a system clock generating circuitry, a subclock

generating circuitry, and two prescalers. The system clock generating circuitry includes an

external clock oscillator, a duty correction circuit, an on-chip oscillator, an RC clock divider, a

clock select circuit, and a system clock divider. The subclock generating circuitry includes a

subclock oscillator, and a subclock divider. The CPG can function as a clock generating circuitry

itself or in combination with an external oscillator. Figure 5.1 shows a block diagram of the clock

pulse generator.

External

clock

oscillator

Duty

correction

circuit

System

clock

divider

Prescaler S

(13 bits)

OSC1

OSC2

φOSC

φ/2

φ/8192

φ/8

φ/16

φ/32

φ/64

On-chip

oscillator

Clock

select

circuit

RC clock

divider

ROSC

φRC

OSC/2

OSC/4

Subclock

oscillator

Subclock

divider

Prescaler W

(5 bits)

System clock generating circuitry

φW

(fW)

φW/2

φW/4

φSUB

φW/8

φW/128

Subclock generating circuitry

Figure 5.1 Block Diagram of Clock Pulse Generator

The system clock (

φ) and subclock (φ

SUB) are basic clocks on which the CPU and on-chip

peripheral modules operate. The system clock is divided into from

φ/2 to φ/8192 by prescaler S.

The subclock is divided into from

W/8 to φW/128 by prescaler W. These divided clocks are

supplied to respective peripheral modules.

HD64F36079G Datasheet(PDF) 103 Page - Renesas Technology Corp

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