38K0 datasheet(83/328 Pages) RENESAS

83 / 328 page

FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 05, 2006

page 66 of 112

38K0 Group

REJ09B0337-0200

HARDWARE

DMA acknowledge

ExDACK

Mch_req

mWR

detection

mWR

detection

012

req

010016

010116

010216

ack

DMA request

ExDREQ

➀

➁➁’

➂’

➂➃

➃

➄

Address ExA0

Chip select ExCS

Read ExRD

Write ExWR

Data DQ0 to DQ7

Internal clock

Receive buffer RXBUF

Operation enabled

Main sequencer

Internal memory access

Acknowledgment of

internal memory access

Memory address

Counter end

Memory channel operation

end interrupt

A0 = “0”

CS = “0”

A0 = “0”

CS = “0”

External I/O configuration register

Set as necessary.

Memory channel operation mode register

MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)

Burst (burst) = “0” (Cycle mode)

Memory address counter

(Example) 010016

End address register

(Example) 010116

EXB interrupt source enable register

MC_ENB (Memory channel operation enable) = “1” (Operation start)

➀ In the memory channel receive mode when the command for enabling operation is written, operation starts (main sequencer starts) and assertion of the

memory channel request which synchronized with a rise of

φ is made.

➁ When the external MCU bus is in the condition of ExCS = “L” and ExA0 = “L” or a fall of ExWR is detected in the condition of ExDACK = “L”, negation of the

memory channel request which synchronized with a rise of

φ is made.

➂ When a rise of ExWR is detected, an internal memory access sequence which synchronized with a rise of φ is activated and a data is written in the internal

memory within two clocks at a minimum.

➃ The memory address counter is increased simultaneously at write completion and assertion of the next memory channel request is made.

➄ When the write operation to the end address has been completed, the memory address counter is increased, but assertion of the next memory channel

request is not made and the memory channel operation end interrupt is generated.

(3) Memory Channel Receiving Operation (1)-

Cycle Mode

Memory channel receiving operation (1) is shown bellow.

Fig. 94 Memory channel receiving operation (1)

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