38K0 datasheet(14/328 Pages) RENESAS

14 / 328 page

Rev.2.00

Oct 05, 2006

page 10 of 13

38K0 Group

REJ09B0337-0200

Fig. 3.3.11 Setup for I/O ports ...................................................................................................... 37

Fig. 3.3.12 Watchdog timer by software ...................................................................................... 38

Fig. 3.4.1 Structure of Port Pi ....................................................................................................... 39

Fig. 3.4.2 Structure of Port Pi direction register ........................................................................ 39

Fig. 3.4.3 Structure of USB control register ................................................................................ 40

Fig. 3.4.4 Structure of USB function enable register ................................................................. 40

Fig. 3.4.5 Structure of USB function address register ............................................................... 40

Fig. 3.4.6 Structure of Frame number register Low ................................................................... 41

Fig. 3.4.7 Structure of Frame number register High .................................................................. 41

Fig. 3.4.8 Structure of USB interrupt source enable register ................................................... 41

Fig. 3.4.9 Structure of USB interrupt source register ................................................................ 42

Fig. 3.4.10 Structure of Endpoint index register ......................................................................... 42

Fig. 3.4.11 Structure of EP00 stage register .............................................................................. 43

Fig. 3.4.12 Structure of EP01 set register .................................................................................. 43

Fig. 3.4.13 Structure of EP02 set register .................................................................................. 44

Fig. 3.4.14 Structure of EP03 set register .................................................................................. 44

Fig. 3.4.15 Structure of EP00 control register 1 ........................................................................ 45

Fig. 3.4.16 Structure of EP01 control register 1 ........................................................................ 45

Fig. 3.4.17 Structure of EP02 control register 1 ........................................................................ 45

Fig. 3.4.18 Structure of EP03 control register 1 ........................................................................ 46

Fig. 3.4.19 Structure of EP00 control register 2 ........................................................................ 46

Fig. 3.4.20 Structure of EP01 control register 2 ........................................................................ 46

Fig. 3.4.21 Structure of EP02 control register 2 ........................................................................ 47

Fig. 3.4.22 Structure of EP03 control register 2 ........................................................................ 47

Fig. 3.4.23 Structure of EP00 control register 3 ........................................................................ 47

Fig. 3.4.24 Structure of EP01 control register 3 ........................................................................ 48

Fig. 3.4.25 Structure of EP02 control register 3 ........................................................................ 48

Fig. 3.4.26 Structure of EP03 control register 3 ........................................................................ 48

Fig. 3.4.27 Structure of EP00 interrupt source register ............................................................ 49

Fig. 3.4.28 Structure of EP01 interrupt source register ............................................................ 50

Fig. 3.4.29 Structure of EP02 interrupt source register ............................................................ 50

Fig. 3.4.30 Structure of EP03 interrupt source register ............................................................ 51

Fig. 3.4.31 Structure of EP00 byte number register .................................................................. 51

Fig. 3.4.32 Structure of EP01 byte number register 0 .............................................................. 51

Fig. 3.4.33 Structure of EP02 byte number register 0 .............................................................. 52

Fig. 3.4.34 Structure of EP03 byte number register 0 .............................................................. 52

Fig. 3.4.35 Structure of EP01 byte number register 1 .............................................................. 52

Fig. 3.4.36 Structure of EP02 byte number register 1 .............................................................. 53

Fig. 3.4.37 Structure of EP03 byte number register 1 .............................................................. 53

Fig. 3.4.38 Structure of Prescaler12, Prescaler X ..................................................................... 53

Fig. 3.4.39 Structure of Timer 1 ................................................................................................... 54

Fig. 3.4.40 Structure of Timer 2, Timer X ................................................................................... 54

Fig. 3.4.41 Structure of Timer X mode register ......................................................................... 55

Fig. 3.4.42 Structure of Transmit/Receive buffer register ......................................................... 55

Fig. 3.4.43 Structure of Serial I/O status register ...................................................................... 56

Fig. 3.4.44 Structure of EXB interrupt source enable register ............................................... 56

Fig. 3.4.45 Structure of EXB interrupt source register .............................................................. 57

Fig. 3.4.46 Structure of EXB index register ................................................................................ 57

Fig. 3.4.47 Structure of Register window 1 ................................................................................. 58

Fig. 3.4.48 Index00[low]; Structure of External I/O configuration register ............................ 58

Fig. 3.4.49 Index01[low]; Structure of Transmit/Receive buffer register ................................. 59

Fig. 3.4.50 Index02[low]; Structure of Memory channel operation mode register ................. 59

List of figures

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