38K0 datasheet(15/328 Pages) RENESAS

15 / 328 page

Rev.2.00

Oct 05, 2006

page 11 of 13

38K0 Group

REJ09B0337-0200

Fig. 3.4.51 Index03[low]; Structure of Memory address counter .............................................. 59

Fig. 3.4.52 Index04[low]; Structure of End address register .................................................... 60

Fig. 3.4.53 Structure of Register window 2 ................................................................................. 60

Fig. 3.4.54 Index00[high]; Structure of External I/O configuration register ........................... 60

Fig. 3.4.55 Index03[high]; Structure of Memory address counter ............................................ 61

Fig. 3.4.56 Index04[high]; Structure of End address register ................................................... 61

Fig. 3.4.57 Structure of AD control register ................................................................................ 61

Fig. 3.4.58 Structure of AD conversion register 1 ..................................................................... 62

Fig. 3.4.59 Structure of AD conversion register 2 ..................................................................... 62

Fig. 3.4.60 Structure of Watchdog timer control register .......................................................... 63

Fig. 3.4.61 Structure of CPU mode register ............................................................................... 63

Fig. 3.4.62 Structure of Interrupt request register 1 .................................................................. 64

Fig. 3.4.63 Structure of Interrupt request register 2 .................................................................. 64

Fig. 3.4.64 Structure of Interrupt control register 1 ................................................................... 65

Fig. 3.4.65 Structure of Interrupt control register 2 ................................................................... 65

Fig. 3.4.66 Structure of Serial I/O control register ..................................................................... 66

Fig. 3.4.67 Structure of UART control register ........................................................................... 66

Fig. 3.4.68 Structure of Baud rate generator .............................................................................. 67

Fig. 3.4.69 Structure of EP01 MAX. packet size register ......................................................... 67

Fig. 3.4.70 Structure of EP02 MAX. packet size register ......................................................... 67

Fig. 3.4.71 Structure of EP03 MAX. packet size register ......................................................... 68

Fig. 3.4.72 Structure of EP00 buffer area set register .............................................................. 68

Fig. 3.4.73 Structure of EP01 buffer area set register .............................................................. 68

Fig. 3.4.74 Structure of EP02 buffer area set register .............................................................. 69

Fig. 3.4.75 Structure of EP03 buffer area set register .............................................................. 69

Fig. 3.4.76 Structure of Port P0 pull-up control register ........................................................... 70

Fig. 3.4.77 Structure of Port P5 pull-up control register ........................................................... 70

Fig. 3.4.78 Structure of Interrupt edge selection register ......................................................... 71

Fig. 3.4.79 Structure of PLL control register .............................................................................. 71

Fig. 3.4.80 Structure of MISRG .................................................................................................... 72

Fig. 3.4.81 Structure of Flash memory control register ............................................................. 72

List of figures

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