38K0 datasheet(86/328 Pages) RENESAS

86 / 328 page

FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 05, 2006

page 69 of 112

38K0 Group

REJ09B0337-0200

HARDWARE

Mch_req

012

req

010016

010116

010216

ack

DMA acknowledge

ExDACK

mRD

detection

mRD

detection

DMA request

ExDREQ

➀

➁

➂’

➂➃

➄

➅

➂’

➅

Address ExA0

Chip select ExCS

Read ExRD

Write ExWR

Data DQ0 to DQ7

Internal clock

Transmit buffer TXBUF

Operation enabled

Transmission completed

Main sequencer

Internal memory access

Acknowledgment of

internal memory access

Memory address

Counter end

Memory channel operation

end interrupt

Dack =

“0”

A0 = “x”

CS = “1”

Dack =

“0”

A0 = “x”

CS = “1”

External I/O configuration register

Set as necessary.

Memory channel operation mode register

MC_DIR[1:0] (Memory channel direction control) = 102 (Transmit mode)

Burst (burst) = “0” (Cycle mode)

Memory address counter

(Example) 010016

End address register

(Example) 010116

EXB interrupt source enable register

MC_ENB (Memory channel operation enable) = “1” (Operation start)

➀ In the memory channel transmit mode when the command for enabling operation is written, operation starts (main sequencer starts) and an internal

memory access sequence which synchronized with a rise of

φ is activated.

➁ A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address

counter is simultaneously increased and assertion of the memory channel request is made.

➂ When the external MCU bus is in the condition of ExCS = “L” and ExA0 = “L” or a fall of ExRD is detected in the condition of ExDACK = “L”, negation of the

memory channel request which synchronized with a rise of

φ is made.

➃ When a rise of ExRD is detected, an internal memory access sequence which synchronized with a rise of φ is activated.

➄ A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address

counter is simultaneously increased and assertion of the memory channel request is made.

When the read operation from the end address has been completed, the transition to the status to wait the memory channel operation end occurs.

➅ When a rise of ExRD is detected, the memory channel operation sequence ends and the memory channel operation end interrupt is generated.

Fig. 97 Memory channel tranmitting operation (1)

(6) Memory Channel Transmitting Operation

(1)-Cycle Mode

Memory channel transmitting operation (1) is shown bellow.

38K0 Datasheet(PDF) 86 Page - Renesas Technology Corp

38K0 Datasheet(HTML) 86 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL