38K0 datasheet(85/328 Pages) RENESAS

85 / 328 page

FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 05, 2006

page 68 of 112

38K0 Group

REJ09B0337-0200

HARDWARE

Mch_req

012

(5)

req

010016

010116

010216

ack

DMA acknowledge

ExDACK

mWR

detection

mWR

detection

DMA request

ExDREQ

➀’

➀

➁’

➁

➁’

➁

Address ExA0

Chip select ExCS

Terminal count ExTC

Write ExWR

Data DQ0 to DQ7

Internal clock

Operation enabled

Receive buffer RxBuf

TC synchronizing

TC end

Main sequencer

Internal memory access

Memory address

Counter end

Burst end

Memory channel operation

end interrupt

mTC

detection

External I/O configuration register

Set as necessary.

Memory channel operation mode register

MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)

Burst (burst) = “1” (Burst mode)

Memory address counter

(Example) 010016

End address register

(Example) 010716

EXB interrupt source enable register

MC_ENB (Memory channel operation enable) = “1” (Operation start)

➀ When a rise of TC is detected, negation of the memory channel request which synchronized with a rise of φ is made.

➁ When the write operation to the end address has been completed, the memory channel operation end interrupt is generated.

Acknowledgment of

internal memory access

Dack =

“0”

A0 = “x”

CS = “1”

Dack =

“0”

A0 = “x”

CS = “1”

(5) Memory Channel Receiving Operation (3)-

Burst Mode (Terminal Count)

Memory channel receiving operation (3) is shown bellow.

Fig. 96 Memory channel receiving operation (3)

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