38K0 datasheet(87/328 Pages) RENESAS

87 / 328 page

FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 05, 2006

page 70 of 112

38K0 Group

REJ09B0337-0200

HARDWARE

Mch_req

012

req

010016

010116

010216

010316

ack

DMA acknowledge

ExDACK

mRD

detection

mRD

detection

DMA request

ExDREQ

➀

➁➂’

➂’

➂

➃➄

➁➃

➄

➅

Address ExA0

Chip select ExCS

Read ExRD

Write ExWR

Data DQ0 to DQ7

Internal clock

Transmit buffer TXBUF

Operation enabled

Transmission completed

Main sequencer

Internal memory access

Acknowledgment of

internal memory access

Memory address

Counter end

Burst end

Memory channel operation

end interrupt

External I/O configuration register

Set as necessary.

Memory channel operation mode register

MC_DIR[1:0] (Memory channel direction control) = 102 (Transmit mode)

Burst (burst) = “1” (Burst mode)

Memory address counter

(Example) 010016

End address register

(Example) 010216

EXB interrupt source enable register

MC_ENB (Memory channel operation enable) = “1” (Operation start)

➀ In the memory channel transmit mode when the command for enabling operation is written, an internal memory access sequence which synchronized with

a rise of

φ is activated.

➁ A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address

counter is simultaneously increased and assertion of the memory channel request is made.

➂ When a rise of ExRD is detected, an internal memory access sequence which synchronized with a rise of φ is activated.

➃ A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address

counter is simultaneously increased.

➄ When the read operation from the end address has been completed, the detection circuit of external read signal (ExRD) operation is enabled and negation

of the memory channel request which synchronized with the following

φ is made.

➅ When a rise of ExRD is detected, the memory channel operation sequence ends and the memory channel operation end interrupt is generated.

Dack =

“0”

A0 = “x”

CS = “1”

Dack =

“0”

A0 = “x”

CS = “1”

Dack =

“0”

A0 = “x”

CS = “1”

Fig. 98 Memory channel tranmitting operation (2)

(7) Memory Channel Transmitting Operation

(2)-Burst Mode

Memory channel transmitting operation (2) is shown bellow.

38K0 Datasheet(PDF) 87 Page - Renesas Technology Corp

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