H83065 datasheet(154/963 Pages) RENESAS

154 / 963 page

Section 6 Bus Controller

Rev. 4.00 Jan 26, 2006 page 132 of 938

REJ09B0276-0400

6.2.5

Bus Control Register (BCR)

BRSTS0

—

RDEA

WAITE

Initial value

Read/Write

R/W

—

R/W

76543210

ICIS1

ICIS0

BROME

BRSTS1

Bit

BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the

area division unit, and enables or disables

WAIT pin input.

BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted

between bus cycles in case of consecutive external read cycles for different areas.

Bit 7

ICIS1

Description

No idle cycle inserted in case of consecutive external read cycles for different

areas

Idle cycle inserted in case of consecutive external read cycles for different

areas

(Initial value)

Bit 6—Idle Cycle Insertion 0 (ICIS0): Selects whether one idle cycle state is to be inserted

between bus cycles in case of consecutive external read and write cycles.

Bit 6

ICIS0

Description

No idle cycle inserted in case of consecutive external read and write cycles

Idle cycle inserted in case of consecutive external read and write cycles

(Initial value)

Bit 5—Burst ROM Enable (BROME): Selects whether area 0 is a burst ROM interface area.

Bit 5

BROME

Description

Area 0 is a basic bus interface area

(Initial value)

Area 0 is a burst ROM interface area

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