H83065 datasheet(155/963 Pages) RENESAS

155 / 963 page

Section 6 Bus Controller

Rev. 4.00 Jan 26, 2006 page 133 of 938

REJ09B0276-0400

Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycle states for the burst

ROM interface.

Bit 4

BRSTS1

Description

Burst access cycle comprises 2 states

(Initial value)

Burst access cycle comprises 3 states

Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a

burst ROM interface burst access.

Bit 3

BRSTS0

Description

Max. 4 words in burst access (burst access on match of address bits above A3)(

Max. 8 words in burst access (burst access on match of address bits above A4)

Bit 2—Reserved: Read-only bit, always read as 1.

Bit 1—Area Division Unit Select (RDEA): Selects the memory map area division units. This bit

is valid in modes 3, 4, and 5, and is invalid in modes 1, 2, 6, and 7.

Bit 1

RDEA

Description

Area divisions are as follows:

Area 0: 2 MB

Area 4: 1.93 MB

Area 1: 2 MB

Area 5: 4 kB

Area 2: 8 MB

Area 6: 23.75 kB

Area 3: 2 MB

Area 7: 22 B

Areas 0 to 7 are the same size (2 MB)

(Initial value)

Bit 0—WAIT Pin Enable (WAITE): Enables or disables wait insertion by means of the

WAIT

pin.

Bit 0

WAITE

Description

WAIT pin wait input is disabled, and the WAIT pin can be used as an

input/output port

(Initial value)

WAIT pin wait input is enabled

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