H83065 datasheet(158/963 Pages) RENESAS

158 / 963 page

Section 6 Bus Controller

Rev. 4.00 Jan 26, 2006 page 136 of 938

REJ09B0276-0400

When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than

000 must not be performed.

Bit 4—Reserved: This bit cannot be modified and is always read as 1.

Bit 3—Burst Access Enable (BE): Enables or disables burst access to DRAM space. DRAM

space burst access is performed in fast page mode.

Bit 3

Description

Burst disabled (always full access)

(Initial value)

DRAM space access performed in fast page mode

Bit 2—RAS Down Mode (RDM): Selects whether to wait for the next DRAM access with the

RAS signal held low (RAS down mode), or to drive the RAS signal high again (RAS up mode),

when burst access is enabled for DRAM space (BE = 1), and access to DRAM is interrupted.

Caution is required when the

HWR and LWR are used as the UCAS and LCAS output pins. For

details, see RAS Down Mode and RAS Up Mode in section 6.5.10, Burst Operation.

Bit 2

RDM

Description

DRAM interface: RAS up mode selected

(Initial value)

DRAM interface: RAS down mode selected

Bit 1—Self-Refresh Mode (SRFMD): Specifies DRAM self-refreshing in software standby

mode.

When any of areas 2 to 5 is designated as DRAM space, DRAM self-refreshing is possible when a

transition is made to software standby mode after the SRFMD bit has been set to 1.

The normal access state is restored when software standby mode is exited, regardless of the

SRFMD setting.

Bit 1

SRFMD

Description

DRAM self-refreshing disabled in software standby mode

(Initial value)

DRAM self-refreshing enabled in software standby mode

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