H83065 datasheet(162/963 Pages) RENESAS

162 / 963 page

Section 6 Bus Controller

Rev. 4.00 Jan 26, 2006 page 140 of 938

REJ09B0276-0400

6.2.9

Refresh Timer Control/Status Register (RTMCSR)

CKS0

———

Initial value

Read/Write

R/W

——

—

R(W)*

R/W

76543210

CMF

CMIE

CKS2

CKS1

Bit

RTMCSR is an 8-bit readable/writable register that selects the refresh timer counter clock. When

the refresh timer is used as an interval timer, RTMCSR also enables or disables interrupt requests.

Bits 7 and 6 of RTMCSR are initialized to 0 by a reset and in the standby modes. Bits 5 to 3 are

initialized to 0 by a reset and in hardware standby mode; they are not initialized in software

standby mode.

Note:

Only 0 can be written to clear the flag.

Bit 7—Compare Match Flag (CMF): Status flag that indicates a match between the values of

RTCNT and RTCOR.

Bit 7

CMF

Description

Clearing conditions

When the chip is reset and in standby mode

Read CMF when CMF = 1, then write 0 in CMF

(Initial value)

Setting condition

When RTCNT = RTCOR

Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt

requested when the CMF flag is set to 1 in RTMCSR. The CMIE bit is always cleared to 0 when

any of areas 2 to 5 is designated as DRAM space.

Bit 6

CMIE

Description

The CMI interrupt requested by CMF is disabled

(Initial value)

The CMI interrupt requested by CMF is enabled

H83065 Datasheet(PDF) 162 Page - Renesas Technology Corp

H83065 Datasheet(HTML) 162 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL